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MC33567 Dual Linear Controller for High Current Voltage Regulation
The MC33567 Dual Linear Power Supply Controller is designed to facilitate power management for motherboard applications where reliable regulation of high current supply planes is required. It provides the Drive, Sense and Control signals to interface two external, N-channel MOSFETs for regulating two different supply planes. Undervoltage short circuit detection places the operation of the system into a protected mode pending removal of the short.
Features http://onsemi.com MARKING DIAGRAM
SO-8 D SUFFIX CASE 751
* Two Independent Regulated Supplies * MC33567-1: 1.515 V - Supply for GTL and AGP Planes * * * * * * *
1.818 V - Supply for I/O Plane and Memory Termination MC33567-2: Dual 2.525 V Supplies for Clock and Memory MC33567-3: 2.3 V - Voltage Supply 1.2 V - Voltage Supply Undervoltage Short Circuit Protection Supply Undervoltage Detection Drive Capability for N-Channel MOSFETs Bypass Function for 3.3 V AGP Card Detection Pb-Free Package May be Available. The G-Suffix Denotes a Pb-Free Lead Finish
8 1
M567x ALYW
x A L Y W
= 1, 2 or 3 = Assembly Location = Wafer Lot = Year = Work Week
PIN CONNECTIONS
DRV1 1 SENSE1 2 SHDN1 3 GND 4 8 VCC 7 DRV2 6 SENSE2 5 SHDN2
Applications
* Motherboards * Dual Power Supplies
VCC 3.3 V 4 GND 3 SHDN1 8 VCC 66 kW Startup & Undervoltage Shutdown REF VCC Control 2 SENSE1 Vout1 1 DRV1 3.3 V
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet.
+ -
+ 8.5 V - UVLO Vin Bypass On (MC33567-1 only) VCC 3.3 V 66 kW REF VCC Control 6 SENSE2 REF 7 DRV2 3.3 V
CL
5 SHDN2
Startup & Undervoltage Shutdown
Vout2
CL
Figure 1. Simplified Block Diagram
(c) Semiconductor Components Industries, LLC, 2003
1
December, 2003 - Rev. 3
Publication Order Number: MC33567/D
MC33567
PIN ASSIGNMENTS AND FUNCTIONS
PIN # 1 2 3 4 5 6 7 8 PIN NAME DRV1 SENSE1 SHDN1 GND SHDN2 SENSE2 DRV2 VCC TTL high level turns on regulation for gate 2. (Internal pull-up to 3.3 V) Sense 2 line. Sense load voltage and provides feedback to regulator. Gate 2 drive. Saturates external FET in bypass mode (MC33567-1 only). Is internally clamped to ground in power down mode. Supply voltage for operation and gate drive output - typically 12 V. PIN DESCRIPTION Gate 1 drive. Is internally clamped to ground in power down mode. Sense 1 line. Sense load voltage and provides feedback to regulator. TTL high level turns on regulation for gate 1. (Internal pull-up to 3.3 V)
MAXIMUM RATINGS (Notes 1, 2 and 3)
Rating Supply Voltage SHUTDOWN Voltage Operating Ambient Temperature Operating Junction Temperature Lead Temperature (Soldering, 10 seconds) Storage Temperature Range Package Thermal Resistance, Junction to Ambient Thermal Resistance, Junction to Case Symbol VCC V SHDN TA TJ TL Tstg RJA (Note 2) RJC Value 12.5 VCC 0 to 80 -5.0 to 125 300 -55 to 150 159 28 Unit Vdc Vdc C C C C C/W C/W
1. ESD Ratings ESD Machine Model protection up to 200 V, class B. ESD Human Body Model protection up to 2000 V, class 2. 2. Minimum pad test board with 5 MIL wide and 2.8 MIL thick copper traces1 inch long. 3. All characterizing done with MTD3055VL N-Channel MOSFETs.
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MC33567
DC ELECTRICAL CHARACTERISTICS
(VCC = 12 V, V SHDN1 = V SHDN2 = 2.0 V, TA = 0C to 80C, typical values shown are for TJ = 25C unless otherwise noted.) Characteristic Supply Voltage Quiescent Current V SHDN1 = V SHDN2 = 0 V V SHDN1 = V SHDN2 = 2.0 V Symbol Vcc IqL IqH Min 9.0 - - Typ 12 5.8 6.3 Max 12.5 9.0 10 Unit V mA
UNDERVOLTAGE LOCKOUT
Undervoltage Lockout Threshold Voltage (VCC Increasing) Hysteresis Voltage (VCC Decreasing) UVLO UVLOVhys 7.0 0.2 8.5 0.5 9.0 0.9 V V
DRIVE OUTPUTS
Drive Output Voltage (Gate to Ground) Drive Output Source Current (TJ = 25C) Gate Drive Output Sink Current (Vsense = 0 V, TJ = 25C) Vdrv Ipkdrv Isink - 10 4.0 10.5 20 7.0 - 30 10 V mA mA
SHUTDOWN INPUTS
Shutdown Threshold Voltage (Drive output on to off, ramp V SHDN to 0 V) Shutdown Threshold Hysteresis (Drive output off to on) Shutdown Disable Time (Drive output on to off, ramp V SHDN to 0 V) Shutdown Input Current (V SHDN = 0 V) SHDNVth SHDNhys SHDNtdis I SHDN 0.8 50 - - 1.13 130 0.5 -50 1.3 200 2.0 - V mV ms mA
SHORT CIRCUIT
Short Circuit/Undervoltage Detect Threshold (Load current increased until output voltage drops activating hiccup mode) Drive Output Response Time to short circuit (Ramp down Vsense to 0 V) Drive Output On Time in hiccup mode (Vsense = 0 V) Drive Output Off Time in hiccup mode (Vsense = 0 V) SCuvd SCtd SCton SCtoff 70 200 0.5 20 75 325 0.97 47.7 80 500 1.5 60 %Vout ms ms ms
OUTPUT REGULATION
Regulator Output Voltage (Vin = 3.3 V, IL = 5.0 mA to 1.3 A) MC33567-1 Output 1 Output 2 MC33567-2 Output 1 Output 2 MC33567-3 Output 1 Output 2 Output Voltage Regulation (IL = 5.0 mA to 1.3 A) V Vout1 Vout2 Vout1 Vout2 Vout1 Vout2 Vreg% 1.773 1.477 2.462 2.462 2.243 1.170 -2.5 1.818 1.515 2.525 2.525 2.300 1.200 - 1.864 1.553 2.589 2.589 2.358 1.230 +2.5 %
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MC33567
OPERATING DESCRIPTION Introduction The MC33567 series is a family of Dual Linear FET Controllers designed for Power Management applications where high current, voltage regulation is needed. Some computer applications include: * 1.2 V - Power Supply * 1.515 V - AGP (Advanced Graphic Port) and GTL+ (Gunning Transistor Logic - Intel's electrical bus technology) * 1.818 V - I/O planes on motherboards * 2.3 V - Power Supply * 2.525 V - Clock and memory The MC33567 provides tight output voltage regulation, (Vout), and incorporates individual SHDN controls for each FET controller and voltage protection by sensing the output voltage.
Output:
Listed below are the SHDN threshold voltage levels and the corresponding regulator output voltages: 1. If the SHDN pin is left open, the output voltage is set to its regulated value. 2. If a voltage less than 0.8 V is applied to the SHDN pin, the output voltage is set to 0 V. 3. If a voltage greater than 1.3 V and less than 4.1 V is applied to the SHDN pin, the output voltage is set to its regulated voltage. 4. If the SHDN voltage is pulled above 4.1 V, the MC33567 enters a Vin bypass mode. In this mode, the MOSFET is fully enhanced and the output voltage is the MOSFET drain voltage (Vin) minus the MOSFET drain-source on voltage VDS(on). This feature is only available on REGULATOR 2 of the MC33567-1. Table 1 summarizes the output voltage options and its relationship with VSHDN.
Table 1. Logic Table for SHDN Pin
Device MC33567-1 REGULATOR 1 V SHDN (V) No Connect t0.8 V u1.3 V No Connect t0.8 V 1.3 V t V SHDN t 4.1 V u 4.1 V Vout (V) 1.818 V 0V 1.818 V 1.515 V 0V 1.515 V Vin-VDS(on) (Bypass Mode) 2.525 V 0V 2.525 V 2.3 V 0V 2.3 V 1.2 V 0V 1.2 V
The MC33567 provides tight output voltage regulation from one or two supply voltages using 2 external N-Channel MOSFETs. Each controller operates independently and regulates the output voltage to a predetermined level (1.2 V, 1.515 V 1.818 V, 2.3 V or 2.525 V). In addition, regulator 2 of the MC33567-1 incorporates a Vin bypass mode on which the external FET is fully enhanced.
Shutdown:
REGULATOR 2
The regulated outputs of the MC33567 can be disabled with the use of the SHDN pin. It also determines the output voltage level. SHDN can be controlled externally from board signals like the AGP or GTL+ as shown in Figure 3.
3.3 V (Vin) AGP Card Type Detection 12 V (VCC) 3.3 V AGP Card Voltage Vout or Vin*
MC33567-2 REGULATOR 1 & REGULATOR 2 MC33567-3 REGULATOR 1
No Connect t0.8 V u1.3 V No Connect t0.8 V u1.3 V No Connect t0.8 V u 1.3 V
REGULATOR 2
10 kW
Undervoltage Detection:
1 2 3 4 8 7
MC33567 6
5
DRV2 SENSE2 SHDN2
*Vin while on bypass mode (MC33567-1 only)
Figure 3. 1.5 V/3.3 V AGP Card Detection
If Vout drops below 75% of the regulated threshold for greater than 250 s or a short circuit condition is present, that output will go into short circuit or Hiccup Mode. While in Hiccup mode, the output is turned ON for 1.0 ms and OFF for 40 ms for a duty cycle of 1:41 as shown in Figure 4. This mode will continue as long as the fault is present. Once the fault is removed, the regulator will resume normal operation.
1 ms 40 ms
Figure 4. Hiccup Mode Duty Cycle
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MC33567
Sense:
If the load is located away from the regulator, the voltage drop on the connecting cable or trace can become significant. The MC33567 provides tight voltage load regulation with varying load currents using it's SENSE feature. As shown in Figure 5, the MC33567 senses the voltage at the load and provides feedback to the regulator. The regulator voltage is then adjusted to compensate for the load changes. It is recommended that the SENSE connection be placed as close as possible to the load. Also, use a separate trace to connect the source of the N-channel MOSFET to the load to avoid interference or coupling with the SENSE signal. The use of the SENSE feature is required for correct device operation. If the SENSE pin is not connected to the load, the output will go into Hiccup mode. The current into the SENSE pin is given by the following equation:
V ISENSE + 100 mA ) out 1.8 kW
Vin
The required RDS(on) can be calculated using the equation below:
RDS(on) v 0.5 Vin * Vout ILOAD
where: Vin = Input Voltage, typically 3.3 V Vout = Regulator Output Voltage (1.2 V, 1.515 V, 1.818 V, 2.3 V, or 2.525 V) ILOAD Load Current = A safety margin of 0.5 was added to account for RDS(on) variations over the operating temperature range.
Stability:
After evaluating the regulator, driver and load system using control theory it is demonstrated that the output capacitor, external driver gain and error amplifier gain bandwidth play an important role on the system stability. To insure system stability the following set of design guidelines should be followed:
Ci + Cgs ) Cgd wf + 1 Ci * Ro
DRV
wp +
Feedback to Regulator 100 mA SENSE 1.8 kW + VOUT - RL ISENSE
1 1)1 * w1 wf
1 20 * 1 )
wa (3 * wp)
(3 * w ) * g1 v Rs v w p * g1 m a m
1 1 Co * Rs w 5 * w ) w a p
Figure 5. Voltage Regulation Using Sense Feature
N-Channel MOSFET Selection:
The MC33567 was characterized using ON Semiconductor's MTD3055VL N-channel MOSFET. Other MOSFETs can be used with the MC33567 as long as power and stability requirements are met.
Power:
A MOSFET with a low drain-source on resistance (RDS(on)) will insure the output voltage is not drastically reduced due to excessive voltage drop across the MOSFET.
where: wf = Driver pole frequency Ci = Input and reverse transfer capacitance when device is off Ro = Regulator output resistance (50 W for the MC33567) wp = Secondary pole for open loop wa = Error amplifier gain bandwidth w1 = Error amp second pole (set w1 = wa, if not specified) Rs = Output capacitor ESR gm = Maximum driver transconductance gain Co = Output capacitance T = Overall loop response time
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MC33567
The output capacitor capacitance and ESR required for using the MTD3055VL as external driver are calculated as follows:
wf + 1 1 + + 10.87 MHz (1240 pF ) 600 pF) * (50 W) Ci * Ro * 1 1 1) 1 1 )1 *+ 5 MHz 10.87 MHz w1 wf (3 * w ) * g1 v Rs v w p * g1 m a m (3 * 3.42 MHz) 1 v Rs v 5 MHz 8.8 mhos
SENSE 1.8 kW RINT ISENSE R2
Adjustable Output Voltage:
The MC33567 will regulate Vout to its preset voltage level, referenced at the sense pin. However, other Vout levels can be obtained scaling the sense voltage. This is done using a resistive network between the load and the sense pin as shown in Figure 6.
Vin
wp +
+ 3.42 MHz 1 20 * 1 ) 1
5 MHz 20 * 1 ) (3 * 3.42 MHz) wa (3 * wp)
DRV +
*
R1 Vout(new) + Vout -
1 * 8.8 mhos 3.8 mW v Rs v 233.2 mW
-
selecting an ESR of 30 mW, we have:
1 1 Co w 5 * w ) w Rs a p Co w 5 1) 1 * 30 mW 5 MHz 3.42 MHz Co w 82.07 mF
Figure 6. Output Voltage Scaling Using Resistive Network
The regulator will increase the load voltage until the SENSE pin voltage reaches the regulator voltage level, Vout. The new output voltage, Vout(new), is calculated as follows:
Vout(new) + Vout ) R1 * Vout ) ISENSE R2
100 F is selected as it is an industry standard value. Please note that if the system is designed to work with several drivers, the system has to be designed around the driver with higher gain to insure stability for all of them. The design guidelines discussed in this section are conservative enough that satisfactory results may be obtained with devices that lie just outside of these guidelines, although deviation from these guidelines will generally cause instability. For a more detailed analysis on linear regulators stability please refer to ON Semiconductor application note AND8037/D.
Please note that in this configuration R2 and the sense internal resistor are in parallel. The parallel combination will reduce the effective resistance of R2. If R2 is in the range of RINT, the parallel combination will be almost half of the original intended value of R2. This will cause Vout(new) to be smaller than calculated using the above equation. This is avoided making R2 as small as possible, probably in the range of 10 to 50 Ohms. Vout(new) is limited by the external driver drain current and its required Gate-Source voltage as well as the Drive Output Voltage, Vdrv. PCB Layout Guidelines It is recommended that the MC33567 be placed as physically close as possible to the external series pass MOSFET transistors. Use short traces to minimize extraneous signals from being induced on the SENSE or DRV line. Also, avoid routing the SENSE line near the load and input current path, as well as the GND return current path to prevent signal coupling.
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MC33567
12 V Power Supply 3.3 V C2 100 F Q1 Vin C1 100 F C3 100 F SENSE1
2
DRV1
1 8 7
VCC DRV2 Q2 SENSE2 LOAD2 C4 100 F SHDN2 SHDN1 LOAD1 AGP Card
SHDN1
3 4
MC33567
6
SHDN2
5
Figure 7. Application Block Diagram Parts List
Qty 4 1 2 Reference C1, C2, C3, C4 U1 Q1, Q2 Part/Description 100 F Electrolytic Capacitor MC33567 MTD3055VL Vendor Various ON Semiconductor ON Semiconductor N-Channel MOSFET Notes
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MC33567
MC33567 TYPICAL CHARACTERISTICS
200 PHASE GAIN/PHASE (dB/) PHASE MARGIN = 48 @ 8 kHz PHASE MARGIN = 60 @ 200 kHz GAIN dB 0 ILOAD = 2 A C = 200 mF RESR = 50 mW -100 10 100 1,000 10,000 100,000 f, FREQUENCY (Hz) 1,000,000 GAIN/PHASE (dB/0) 200 PHASE PHASE MARGIN = 85 @ 8 kHz PHASE MARGIN = 48 @ 500 kHz GAIN dB 0 ILOAD = 2 A C = 200 mF RESR = 200 mW -100 10 100 1,000 10,000 100,000 f, FREQUENCY (Hz) 1,000,000
100
100
Figure 8. Gain-Phase Plot for Output Capacitor with 50 mW ESR
VOUT1, REGULATOR 1 OUTPUT VOLTAGE (V) 1.840 1.835 1.830 1.825 1.820 1.815 1.810 1.805 1.800 1.795 1.790 -10 IL = 5 mA IL = 1.3 A Gate Drive 2 Open VOUT2, REGULATOR 2 OUTPUT VOLTAGE (V) 1.540
Figure 9. Gain-Phase Plot for Output Capacitor with 200 mW ESR
Gate Drive 2 Open
1.535 1.530 1.525 1.520 1.515 1.510 IL = 5 mA IL = 1.3 A
1.505 1.500 1.495 0 10 20 30 40 50 60 70 80 90
0
10
20
30
40
50
60
70
80
90
1.490 -10
TA,TEMPERATURE (C)
TA,TEMPERATURE (C)
Figure 10. Regulator 1 (Suffix 1) Output Voltage vs. Ambient Temperature
Figure 11. Regulator 2 (Suffix 1) Output Voltage vs. Ambient Temperature
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MC33567
SCUVD, SHORT CIRCUIT/UNDERVOLTAGE DETECT THRESHOLD (V) SCUVD, SHORT CIRCUIT/UNDERVOLTAGE DETECT THRESHOLD (V)
1.40 Regulator 1 1.35 1.30 1.25 1.20 1.15 1.10 -10 Regulator 2
1.9 Regulator 1 1.7 1.5 1.3 1.1 0.9 0.7 -10 Regulator 2
0
10
20
30
40
50
60
70
80
90
0
10
20
30
40
50
60
70
80
90
TA,TEMPERATURE (C)
TA,TEMPERATURE (C)
Figure 12. Short Circuit/Undervoltage Detect Threshold (Suffix 1) vs. Ambient Temperature
VOUT1, REGULATOR 1 OUTPUT VOLTAGE (V) VOUT2, REGULATOR 2 OUTPUT VOLTAGE (V)
Figure 13. Short Circuit/Undervoltage Detect Threshold (Suffix 3) vs. Ambient Temperature
2.320 2.315 2.310 2.305 2.300 2.295 2.290 2.285 2.280 2.275 2.270 -10
Gate Drive 2 Open IL = 1.3 A
1.200 1.215 1.210 1.205 1.200 1.195 1.190 1.185 1.180 1.175 1.170 -10
Gate Drive 2 Open
IL = 5 mA IL = 1.3 A
IL = 5 mA
0
10
20
30
40
50
60
70
80
90
0
10
20
30
40
50
60
70
80
90
TA,TEMPERATURE (C)
TA,TEMPERATURE (C)
Figure 14. Regulator 1 (Suffix 3) Output Voltage vs. Ambient Temperature
ISINK, GATE DRIVE SINK CURRENT (mA)
Figure 15. Regulator 2 (Suffix 3) Output Voltage vs. Ambient Temperature
8.0 Iq, QUIESCENT CURRENT (mA) 7.6 Regulator 1 7.2 Regulator 2 6.8 6.4 6.0 5.6 -10
6.4 6.3 6.2 6.1 6.0 5.9 5.8 5.7 5.6 5.5 5.4 -10 0 10 20 30 40 50 60 70 80 90 Quiescent Current with both SHDNs Low IL = 50 mA Quiescent Current with both SHDNs High
0
10
20
30
40
50
60
70
80
90
TA,TEMPERATURE (C)
TA,TEMPERATURE (C)
Figure 16. Gate Drive Sink Current vs. Ambient Temperature
Figure 17. Quiescent Current vs. Ambient Temperature
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MC33567
VHYS, UVLO HYSTERESIS VOLTAGE (mV) 8.6 UVLO, UNDERVOLTAGE LOCKOUT THRESHOLD VOLTAGE (V) 8.5 8.4 8.3 8.2 8.1 8.0 7.9 -10 Minimum Operating Threshold Startup Threshold 520 510 500 490 480 470 460 450 440 -10 0 10 20 30 40 50 60 70 80 90
0
10
20
30
40
50
60
70
80
90
TA,TEMPERATURE (C)
TA,TEMPERATURE (C)
Figure 18. Undervoltage Lockout Threshold vs. Ambient Temperature
Figure 19. UVLO Hysteresis Voltage vs. Ambient Temperature
VDRV, DRIVE OUTPUT VOLTAGE (V)
10.70 10.65 10.60
VSHDN = 4.2 V VCC = 12 V
SCTOFF, DRIVE OUTPUT OFF TIME IN HICCUP MODE (ms) 50 60 70 80 90
10.75
50.0 49.5 49.0 48.5 48.0 47.5 47.0 46.5 46.0 45.5 45.0 -10 0 10 20 30 40 50 60 70 80 90
Series 1
10.55 10.50 10.45 10.40
10.35 10.30 -10 0 10 20 30 40
TA,TEMPERATURE (C)
TA,TEMPERATURE (C)
Figure 20. Regulator 2 Maximum Gate Voltage vs. Ambient Temperature
Figure 21. Drive Output Off Time in Hiccup Mode vs. Ambient Temperature
1.06 SCTON, DRIVE OUTPUT ON TIME IN HICCUP MODE (ms) 1.04 1.02 1.00 0.98 0.96 0.94 0.92 0.90 -10 0 10 20 30 40 50 60 70 80 90
TA,TEMPERATURE (C)
Figure 22. Drive Output On Time in Hiccup Mode vs. Ambient Temperature
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MC33567
ORDERING INFORMATION
Device MC33567D-1 MC33567D-1R2 MC33567D-1R2G MC33567D-2 MC33567D-2R2 MC33567D-3 MC33567D-3R2 Package SO-8 SO-8 SO-8 (Pb-Free) SO-8 SO-8 SO-8 SO-8 Shipping 98 Units/Rail 2500/Tape & Reel 2500/Tape & Reel 98 Units/Rail 2500/Tape & Reel 98 Units/Rail 2500/Tape & Reel
Vout1 1.818 V 1.818 V 1.818 V 2.525 V 2.525 V 2.300 V 2.300 V
Vout2 1.515 V or Vin* 1.515 V or Vin* 1.515 V or Vin* 2.525 V 2.525 V 1.200 V 1.200 V
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *While on bypass mode.
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MC33567
PACKAGE DIMENSIONS
SO-8 D SUFFIX PLASTIC SOIC PACKAGE CASE 751-07 ISSUE AA
-X- A
8 5
B
1 4
S
0.25 (0.010)
M
Y
M
-Y- G C -Z- H D 0.25 (0.010)
M SEATING PLANE
K
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDAARD IS 751-07 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244
N
X 45 _
0.10 (0.004)
M
J
ZY
S
X
S
DIM A B C D G H J K M N S
SOLDERING FOOTPRINT*
1.52 0.060 7.0 0.275 4.0 0.155
0.6 0.024
1.270 0.050
SCALE 6:1 mm inches
Figure 23. SO-8
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Phone: 81-3-5773-3850 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative.
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MC33567/D

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